Gallium nitride (GaN) semiconductor devices are increasingly desirable for power semiconductor devices because of their ability to carry large current and support high voltages. Development of these devices has generally been aimed at high power/high frequency applications. Devices fabricated for these types of applications are based on general device structures that exhibit high electron mobility and are referred to variously as heterojunction field effect transistors (HFET), high electron mobility transistors (HEMT), or modulation doped field effect transistors (MODFET).
A GaN HEMT device includes a nitride semiconductor with at least two nitride layers. Different materials formed on the semiconductor or on a buffer layer cause the layers to have different band gaps. The different material in the adjacent nitride layers also causes polarization, which contributes to a conductive two-dimensional electron gas (2DEG) region near the junction of the two layers, specifically in the layer with the narrower band gap.
The nitride layers that cause polarization typically include a barrier layer of AlGaN adjacent to a layer of GaN to include the 2DEG, which allows charge to flow through the device. This barrier layer may be doped or undoped. Because the 2DEG region exists under the gate at zero gate bias, most nitride devices are normally on, or depletion mode devices. If the 2DEG region is depleted, i.e. removed, below the gate at zero applied gate bias, the device can be an enhancement mode device. Enhancement mode devices are normally off and are desirable because of the added safety they provide and because they are easier to control with simple, low cost drive circuits. An enhancement mode device requires a positive bias applied at the gate in order to conduct current.
FIG. 1 illustrates a cross-sectional view of a conventional enhancement mode GaN transistor 100 with a single layer of a surface passivating insulator (layer) 108, and is more fully described in U.S. Pat. No. 8,076,698, issued to Ueda et al. Device 100 of FIG. 1 includes substrate 101 that can be composed of silicon (Si), silicon carbide (SiC), sapphire, or other material, transition layers 102 composed of AlN and AlGaN that is about 0.1 to about 1.0 μm in thickness, buffer material 103 composed of GaN that is about 0.5 to about 10 μm in thickness, barrier material 104 composed of AlGaN where the Al to Ga ratio is about 0.1 to about 0.5 with thickness from about 0.005 to about 0.03 μm, low-doped p-type AlGaN 105, heavily doped p-type GaN 106, isolation region 107, passivation layer/region 108, ohmic contact metals 109 and 110 for the source and drain, typically composed of Ti and Al with a capping metal such as Ni and Au, and gate metal 111 typically composed of a nickel (Ni) and gold (Au) metal contact over the p-type GaN gate.
FIG. 2 illustrates a cross-section of a prior art GaN transistor device without a surface passivating insulator, and is more fully more described in U.S. Pat. No. 8,350,294, issued to Lidow et al. GaN transistor 1 is formed on a substrate 31 that may comprise, for example, silicon Si, silicon carbide SiC or sapphire. Over and in contact with the substrate 31 are transition layers 32. Transition layers 32 comprise AlN or AlGaN, with a thickness of between 0.1 to 1.0 μm. A buffer layer 33 separates the transition layers 32 from a barrier layer 34. The buffer layer 33 is preferably formed of InAlGaN with any concentration of In and Al (including 0% In and/or Al) and has a thickness between 0.5 and 3 μm. The barrier layer 34 is formed of AlGaN and has a thickness between 0.005 and 0.03 μm and an Al percentage of about 10% to 50%. Source and drain contacts 35, 36 are disposed over the barrier layer. Source and drain contacts are formed of Ti or Al with a capping metal such as Ni and Au or Ti and TiN. A gate contact 37, formed of Ta, Ti, TiN, W, or WSi2, and having a thickness of between 0.05 and 1.0 μm, is provided between the source and drain contacts. A compensated semiconductor layer 38 is formed over the barrier layer 34 and under the gate contact 37. Compensated semiconductor layer 38 preferably comprises AlGaN or GaN with a deep level passivated p-type impurity such as, for example, Mg, Zn, Be, Cd, or Ca. Buffer layer 33 and barrier layer 34 are made of a III Nitride material, such as InxAlyGa(1-x-y)N, where x+y≤1. The high doping level of compensated layer 38 leads to an enhancement mode device. In addition, using a compensated semiconductor layer 38 leads to low gate leakage during device operation. Finally, the insulating nature of compensated layer 38 reduces the gate capacitance of the device.
The conventional GaN transistors shown in FIGS. 1 and 2 have several disadvantages. In most Si devices, the insulator/barrier interface (such as in FIG. 1) is not a critical parameter. In GaN transistors, however, it is a critical parameter, dominating device performance. A single layer of a surface passivating insulator, such as passivation layer 108 in FIG. 1, can be made to minimize leakage current and gate to drain capacitance, or it can be made to give high electron density in the channel and low drain field. But the single insulating passivation layer cannot be made to do both at the same time.
It therefore would be desirable to provide a GaN transistor that minimizes or eliminates leakage current and gate to drain capacitance, and that exhibits high electron density in the channel and low drain field, during device conduction.